Date: Thursday 27 March 2014
Time: 08:30 - 10:00
Location / Room: Exhibition Theatre
Organisers:
Hung-Ming Chen, National Chiao Tung University, Taiwan, Ta
Yiyu Shi, Missouri University of Science & Technology, US
Chair:
Tsung-Yi Ho, CSIE, NCKU, TW
Co-Chair:
Hung-Ming Chen, National Chiao Tung University, TW
Energy efficiency has emerged as a major barrier to performance scalability for modern processors. On the other hand, significant breakthroughs have been achieved in memory technologies recently. As such, the fascinating idea of memcomputing (i.e., use memory for computation purposes) has drawn wide attention from both academia and industry as an effective remedy. Compared with conventional logic computing, memory array provides large set of parallel resources with high bandwidth, which can be configured to perform computing in spatial/temporal manner leading to dramatic reduction in processor-memory traffic. Moreover, memory computing brings the computing engine close to the data, thus drastically minimizing the von Neumann bottleneck. Finally, it exploits the advances in memory technologies and integration approaches (e.g. 3D integration) to achieve better technology scalability. This special session offers a broad-spectrum retreat (devices, processes and systems) on this hot topic to the general CAD community, hoping to inspire more contributions from the design automation perspective.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 08:30 | 9.8.1 | MEMCOMPUTING: A BRAIN-INSPIRED COMPUTING PARADIGM Speaker: Yuriy Pershin, University of South Carolina, US |
| 09:00 | 9.8.2 | MSIM: A GENERAL CYCLE ACCURATE SIMULATION PLATFORM FOR MEMCOMPUTING STUDIES Speakers: Chun Zhang1, Peng Deng2, Hui Geng1, Jianming Liu1, Qi Zhu2, Jinjun Xiong3 and Yiyu Shi1 1Missouri University of Science and Technology, US; 2University of California, Riverside, US; 3IBM T.J. Watson Research Center, US Abstract The lack of accurate yet open to public simulation infrastructure has puzzled researchers in the memcomputing area for sometime. In this paper, we propose for the first time a full tool chain called MSim that supports the cycle-accurate microarchitecture level simulation for memcomputing studies. With MSim, the performance gains of utilizing memcomputing for arbitrary applications on user configurable computer system architectures can be evaluated in high accuracy. In addition, MSim provides flexible interfaces with pervasive object-oriented design, which makes it well-suited as a good base platform for researchers to explore new memcomputing technologies. |
| 09:30 | 9.8.3 | ENERGY-EFFICIENT HARDWARE ACCELERATION THROUGH COMPUTING IN THE MEMORY Speakers: Somnath Paul1, Robert Karam2, Swarup Bhunia2 and Ruchir Puri3 1Intel Corporation, US; 2Case Western Reserve University, US; 3IBM Watson Research Center, US Abstract Energy-efficiency has emerged as a major barrier to performance scalability for modern processors. We note that significant part of processor's energy requirement is contributed by processor-memory communication. To address the energy issue in processors, we propose a novel hardware accelerator framework that transforms high-density memory array into a configurable computing resource to accelerate variety of tasks - both compute- and data-intensive. It exploits the block-based architecture of nanoscale memory to create a spatially connected array of lightweight processors, each of which uses a memory block as its local memory. The proposed framework provides some unique advantages for hardware acceleration compared to conventional accelerators: 1) memory array provides large set of parallel resources with high bandwidth, which can be configured to perform computing in spatio/temporal manner leading to dramatic reduction in processor-memory traffic; 2) it brings the computing engine close to the data, thus drastically minimizing the von Neumann bottleneck; 3) finally, it exploits the advances in memory technologies and integration approaches e.g. 3D integration to achieve better technology scalability compared to alternative reconfigurable accelerator platforms. Simulation results for several data-intensive applications show that the proposed computing approach provides significant improvement in energy-efficiency compared to software while achieving significantly lower hardware overhead. |
| 10:00 | End of session Coffee Break in Exhibition Area On Tuesday-Thursday the coffee and lunch breaks will be located in the Exhibition Area (Terrace Level). |