Date: Wednesday 26 March 2014
Time: 17:00 - 18:30
Location / Room: Konferenz 6
Organiser:
Michael Huebner, Ruhr-University Bochum, Ge
Chair:
Michael Huebner, Ruhr-University Bochum, DE
To face with the power/utilization wall, Near-Threshold Computing (NTC) has emerged as one of the most promising approach to achieve an order of magnitude improvement or more in energy efficiency of microprocessors and reconfigurable hardware. NTC takes advantage of the quadratic relation between the supply voltage (Vdd) and the dynamic power, by lowering the supply voltage of chips to a value only slightly higher than the threshold voltage.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 17:00 | 8.2.1 | EXTREME-SCALE COMPUTER ARCHITECTURE: ENERGY EFFICIENCY FROM THE GROUND UP Speaker: Josep Torrellas, University of Illinois Urbana Champaign, US Abstract As we move to integration levels of 1,000-core processor chips, it is clear that energy and power consumption are the most formidable obstacles. To construct such a chip, we need to rethink the whole compute stack from the ground up for energy efficiency --- and attain Extreme-Scale Computing. First of all, we want to operate at low voltage, since this is the point of maximum energy efficiency. Unfortunately, in such an environment, we have to tackle substantial process variation. Hence, it is important to design efficient voltage regulation, so that each region of the chip can operate at the most efficient voltage and frequency point. At the architecture level, we require simple cores organized in a hierarchy of clusters. Moreover, we also need techniques to reduce the leakage of on-chip memories and to lower the voltage guardbands of logic. Finally, data movement should be minimized, through both hardware and software techniques. With a systematic approach that cuts across multiple layers of the computing stack, we can deliver the required energy efficiencies. |
| 17:30 | 8.2.2 | VOLTAGE ISLAND MANAGEMENT IN NEAR THRESHOLD MANYCORE ARCHITECTURES TO MITIGATE DARK SILICON Speakers: Cristina Silvano1, Gianluca Palermo1, Sotirios Xydis2 and Ioannis Stamelakos1 1Politecnico di Milano, IT; 2National Technical University of Athens, GR Abstract The power-wall problem driven by the stagnation of supply voltages in deep-submicron technology nodes, is now the major scaling barrier for moving towards the manycore era. Although the technology scaling enables extreme volumes of computational power, power budget violations will permit only a limited portion to be actually exploited, leading to the so called dark silicon. Near-Threshold voltage Computing (NTC) has emerged as a promising approach to overcome the manycore power-wall, at the expenses of reduced performance values and higher sensitivity to process variations. Given that several application domains operate over specific performance constraints, the performance sustainability is considered a major issue for the wide adoption of NTC. Thus, in this paper, we investigate how performance guarantees can be ensured when moving towards NTC manycores through variability-aware voltage and frequency allocation schemes. We propose three aggressive NTC voltage tuning and allocation strategies, showing that STC performance can be efficiently sustained or even optimized at the NTC regime. Finally, we show that NTC highly depends on the underlying workload characteristics, delivering average power gains of 65% for thread-parallel workloads and up to 90% for process-parallel workloads, while offering an extensive analysis on the effects of different voltage tuning/allocation strategies and voltage regulator configurations. |
| 18:00 | 8.2.3 | RESOLVING THE MEMORY BOTTLENECK FOR SINGLE SUPPLY NEAR-THRESHOLD COMPUTING Speakers: Tobias Gemmeke1, Mohamed Sabry2, Jan Stuijt1, Praveen Raghavan3, Francky Catthoor3 and David Atienza2 1Holst-Centre / imec, NL; 2ESL-EPFL, CH; 3imec, BE Abstract This papers focuses on state-of-the-art memory designs for NTC. It presents new ways to design reliable low-voltage memories cost-effectively by reusing available cell libraries, or by adding a digital wrapper around existing commercially available memories. The approach is based on modeling at system level supported by silicon measurement on a test chip in a 40nm low-power processing technology. Advanced monitoring, control and run-time error mitigation schemes enable the operation of these memories at the same optimal near-Vt voltage level as the digital logic. Reliability degradation is thus overcome and this opens the way to solve the memory bottleneck in NTC systems. Starting at the available silicon measurements, the analysis is extended to a future 14 and 10 nm technology nodes. |
| 18:30 | End of session | |
| 19:30 | DATE Party in "Gläserne Manufaktur" of the Volkswagen AG The DATE Party is again scheduled on the second conference day, Wednesday, March 26, 2014, starting from 19:30 h. This year, it will take place in one of Dresden's most exciting and modern buildings, the "Gläserne Manufaktur" of the car manufacturer Volkswagen AG (www.glaesernemanufaktur.de/en/). The party will feature a flying buffet style dinner with various catering points and accompanying drinks. Light background music and the possibility of guided visits through the extraordinary premises will round off the evening. It provides a perfect opportunity to meet friends and colleagues in a relaxed atmosphere while enjoying local amenities. Please kindly note that it is no seated dinner. All delegates, exhibitors and their guests are encouraged to attend the party. Please be aware that entrance is only possible with a party ticket. Each full conference registration includes a ticket for the DATE Party. Additional tickets can be purchased on-site at the registration desk (subject to availability of tickets). Ticket price for the full Evening Social Programme: 75 € per person. |