Date: Wednesday 26 March 2014
Time: 14:30 - 16:00
Location / Room: Konferenz 5
Chair:
Erik Jan Marinissen, IMEC, BE
Co-Chair:
Hans-Joachim Wunderlich, Univ. of Stuttgart, DE
This session covers topics that blend test with fault tolerance, security, and logic placement. As the area of IC test matures the core technology is adapting to the needs of the design and its implementation. As we move forward to advanced nodes in manufacturing the need to tolerate errors could blend with test methods. Test structures provide access to key design IP which is of concern in some situations. Papers in this session address solutions in IC Test for security.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 14:30 | 7.7.1 | BIT-FLIPPING SCAN - A UNIFIED ARCHITECTURE FOR FAULT TOLERANCE AND OFFLINE TEST Speakers: Michael Imhof1 and Hans-Joachim Wunderlich2 1Institute of Computer Architecture and Computer Engineering, University of Stuttgart, DE; 2University of Stuttgart, DE Abstract Test is an essential task since the early days of digital circuits. Every produced chip undergoes at least a production test supported by on-chip test infrastructure to reduce test cost. Throughout the technology evolution fault tolerance gained importance and is now necessary in many applications to mitigate soft errors threatening consistent operation. While a variety of effective solutions exists to tackle both areas, test and fault tolerance are often implemented orthogonally, and hence do not exploit the potential synergies of a combined solution. The unified architecture presented here facilitates fault tolerance and test by combining a checksum of the sequential state with the ability to flip arbitrary bits. Experimental results confirm a reduced area overhead compared to a orthogonal combination of classical test and fault tolerance schemes. In combination with heuristically generated test sequences the test application time and test data volume are reduced significantly. |
| 15:00 | 7.7.2 | TESTING PUF-BASED SECURE KEY STORAGE CIRCUITS Speakers: Mafalda Cortez1, Gijs Roelofs1, Said Hamdioui1 and Giorgio Di Natale2 1Delft University of Technology, NL; 2LIRMM, FR Abstract Design for test is an integral part of any VLSI chip. However, for secure systems extra precautions have to be taken to prevent that the test circuitry could reveal secret information. This paper addresses secure test for Physical Unclonable Function based systems. In particular it provides the testability analysis and a secure Built-In Self-Test (BIST) solution for Fuzzy Extractor (FE) which is the main component of PUF-based systems. The scheme targets high stuck-at-fault (SAF) coverage by performing scan-chain free functional testing, to prevent scan-chain abuse for attacks. The scheme reuses existing FE sub-blocks (for pattern generation and compression) to minimize the area overhead. The scheme is integrated in FE design and simulated; the results show that a SAF fault coverage of 95.1% can be realized with no more than 50k clock cycles at the cost of a negligible area overhead of only 2.2%. Higher fault coverage is possible to realize at extra cost. |
| 15:30 | 7.7.3 | MAKING IT HARDER TO UNLOCK AN LSIB: HONEYTRAPS AND MISDIRECTION IN A P1687 NETWORK Speakers: Adam Zygmontowicz1, Jennifer Dworak1, Al Crouch2 and John Potter2 1Southern Methodist University, US; 2ASSET InterTech, US Abstract Today's chips often contain a wealth of embedded instruments and data, including sensors, hardware monitors, built-in self test (BIST) engines, and chip IDs, among others. IEEE P1687 was specifically designed to provide access to such instruments in an efficient manner, and some companies are already implementing the proposed standard on their chips. However, while such instruments provide valuable information and features to authorized users who need to harness them for test, debug, diagnosis, and possibly counterfeit detection, it may be desirable to restrict unauthorized access to them through the P1687 network. Previous work has proposed replacing some of the segment insertion bits (SIBs), which add scan path segments in a P1687 network, with locking SIBs (LSIBs). LSIBs use the data that is naturally scanned through the network as keys to hide instruments from attackers. However, that previous work did not investigate many of the techniques and structures that can be used to significantly increase the time an attacker is likely to need to unlock LSIBs and gain access to hidden instruments. In this work, we explore some of these techniques and show how simple modifications to a P1687 network protected with LSIBs can significantly increase the difficulty an attacker faces in attempting to access protected instruments. |
| 15:45 | 7.7.4 | CO-OPTIMIZATION OF MEMORY BIST GROUPING, TEST SCHEDULING, AND LOGIC PLACEMENT Speakers: Ilgweon Kang and Andrew B. Kahng, UC San Diego, US Abstract Built-in self-test (BIST) is a well-known design technique in which part of a circuit is used to test the circuit itself. BIST plays an important role for embedded memories, which do not have pins or pads exposed toward the periphery of the chip for testing with automatic test equipment. With the rapidly increasing number of embedded memories in modern SOCs (up to hundreds of memories in each hard macro of the SOC), product designers incur substantial costs of test time (subject to possible power constraints) and BIST logic physical resources (area, routing, power). However, only limited previous work addresses the physical design optimization of BIST logic; notably, Chien et al. [7] optimize BIST design with respect to test time, routing length, and area. In our work, we propose a new three-step heuristic approach to minimize test time as well as test physical layout resources, subject to given upper bounds on power consumption. A key contribution is an integer linear programming ILP framework that determines optimal test time for a given cluster of memories using either one or two BIST controllers, subject to test power limits and with full comprehension of available serialization and parallelization. Our heuristic approach integrates (i) generation of a hypergraph over the memories, with test time-aware weighting of hyperedges, along with top-down, FM-style min-cut partitioning; (ii) solution of an ILP that comprehends parallel and serial testing to optimize test scheduling per BIST controller; and (iii) placement of BIST logic to minimize routing and buffering costs. When evaluated on hard macros from a recent industrial 28nm networking SOC, our heuristic solutions reduce test time estimates by up to 11.57% with strictly fewer BIST controllers per hard macro, compared to the industrial solutions. |
| 16:00 | End of session Coffee Break in Exhibition Area On Tuesday-Thursday the coffee and lunch breaks will be located in the Exhibition Area (Terrace Level). |