Date: Wednesday 26 March 2014
Time: 14:30 - 16:00
Location / Room: Konferenz 4
Chair:
Wang Yi, Uppsala University, SE
Co-Chair:
Petru Eles, Linköping University, SE
This session includes three papers. The first uses data mining techniques to detect performance bottlenecks to improve the scalability of multicore platforms for embedded applications. The second proposes to use regular expressions for specifying the patterns of deadline misses and hits to relax schedulability analysis for cyber physical systems. The third presents an approach to the scheduling of streaming applications, considering latency constraints and minimization of the number of processors required.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 14:30 | 7.6.1 | (Best Paper Award Candidate) SCALABILITY BOTTLENECKS DISCOVERY IN MPSOC PLATFORMS USING DATA MINING ON SIMULATION TRACES Speakers: Sofiane Lagraa1, Alexandre Termier2 and Frédéric Pétrot1 1Grenoble institute of Technologie, FR; 2University of Joseph Fourier, FR Abstract Nowadays, a challenge faced by many developers is the profiling of parallel applications so that they can scale over more and more cores. This is especially critical for embedded systems powered by Multi-Processor System-on-Chip (MPSoC), where ever demanding applications have to run smoothly on numerous cores, each with modest computational performance. The reasons for the lack of scalability of parallel applications are numerous, and it can be time consuming for a developer to pinpoint the correct one. In this paper, we propose a fully automatic method which detects the instructions of the code which lead to a lack of scalability. The method is based on data mining techniques exploiting low level execution traces produced by MPSoC simulators. Our experiments show the accuracy of the proposed technique on five different kinds of applications, and how the information reported can be exploited by application developers. |
| 15:00 | 7.6.2 | COMPUTING A LANGUAGE-BASED GUARANTEE FOR TIMING PROPERTIES OF CYBER-PHYSICAL SYSTEMS Speakers: Neil Dhruva, Pratyush Kumar, Georgia Giannopoulou and Lothar Thiele, ETH Zurich, CH Abstract Real-time systems are often guaranteed in terms of schedulability, which verifies whether or not all jobs meet their deadlines. However, such a guarantee can be insufficient in certain applications. In this paper, we propose a method to compute a language-based guarantee which provides a more detailed description of the deadline miss patterns of an observed task. The only requirement of our method is that the timing behavior of the real-time system be modelled by a network of timed automata. We compute the language-based guarantee by constructing an equivalent finite state automaton in an iterative manner, using a counter-example guided procedure. We illustrate the language-based guarantee for two applications: design of a networked control system and scheduling in a mixed criticality system. In both cases, we show that the language-based guarantee leads to a more efficient design than the schedulability guarantee. |
| 15:30 | 7.6.3 | RESOURCE OPTIMIZATION FOR CSDF-MODELED STREAMING APPLICATIONS WITH LATENCY CONSTRAINTS Speakers: Di Liu1, Jelena Spasic1, Jiali Teddy Zhai1, Todor Stefanov1 and Gang Chen2 1Leiden University, NL; 2Technical University Munich, DE Abstract In this paper, we study the problem of minimizing the number of processors required for scheduling latency-constrained streaming applications modeled as CSDF graphs, where the actors of a CSDF are executed as strictly periodic tasks. We formalize the problem and prove that due to the strict periodicity of actors the problem is an integer convex programming problem, that can be solved efficiently by using an existing convex programming solver. We evaluate our solution approach on a set of 13 real-life streaming applications modeled as CSDF graphs and demonstrate that it can reduce the number of processors in more than 52% of the conducted experiments in comparison to an existing approach. |
| 16:00 | IP3-17, 163 | A LAYERED APPROACH FOR TESTING TIMING IN THE MODEL-BASED IMPLEMENTATION Speakers: BaekGyu Kim1, Hyeon I Hwang2, Taejoon Park2, Sanghyuk Son2 and Insup Lee1 1University of Pennsylvania, US; 2Daegu Gyeongbuk Institute of Science & Technology, KR Abstract The model-based implementation is to derive an implementation from a model that has been shown to meet requirements. Even though this approach can be used to guarantee that an implementation satisfies functional requirements that are shown to be correct at the model level, it is still challenging to assure timing requirements at the implementation level. We propose a layered approach in testing timing requirements conformance of implemented systems developed by model-based implementation. In our approach, the abstraction boundary of the implemented system is formally defined using Parnas' four-variables model. Then, the proposed approach tests timing aspects of the interaction between the auto-generated code and the target platform-dependent code based on the four-variables. This approach aims at not only detecting the timing requirement violation, but also at measuring delay-segments that contribute to the timing deviation of the implemented system w.r.t. the model. We show the case study of testing timing requirements of an infusion pump system to illustrate the applicability of the proposed framework. |
| 16:01 | IP3-18, 222 | MODEL-BASED PROTOCOL LOG GENERATION FOR TESTING A TELECOMMUNICATION TEST HARNESS USING CLP Speakers: Kenneth Balck1, Olga Grinchtein1 and Justin Pearson2 1Ericsson AB, SE; 2Uppsala University, SE Abstract Within telecommunications development it is vital to have frameworks and systems to replay complicated scenarios on equipment under test, often there are not enough available scenarios. In this paper we study the problem of testing a test harness, which replays scenarios and analyses protocol logs for the Public Warning System service, which is a part of the Long Term Evolution (LTE) 4G standard. Protocol logs are sequences of messages with timestamps; and are generated by different mobile network entities. In our case study we focus on user equipment protocol logs. In order to test the test harness we require that logs have both incorrect and correct behaviour. It is easy to collect logs from real system runs, but these logs do not show much variation in the behaviour of system under test. We present an approach where we use constraint logic programming (CLP) for both modelling and test generation, where each test case is a protocol log. In this case study, we uncovered previously unknown faults in the test harness. |
| 16:02 | IP3-19, 294 | TIME-DECOUPLED PARALLEL SYSTEMC SIMULATION Speakers: Jan Weinstock1, Christoph Schumacher1, Rainer Leupers1, Gerd Ascheid1 and Laura Tosoratto2 1RWTH Aachen, DE; 2Istituto Nazionale di Fisica Nucleare, Sezione di Roma, IT Abstract With increasing system size and complexity, designers of embedded systems face the challenge of efficiently simulating these systems in order to enable target specific software development and design space exploration as early as possible. Today's multicore workstations offer enormous computational power, but traditional simulation engines like the OSCI SystemC kernel only operate on a single thread, thereby leaving a lot of computational potential unused. Most modern embedded system designs include multiple processors. This work proposes SCope, a SystemC kernel that aims at exploiting the inherent parallelism of such systems by simulating the processors on different threads. A lookahead mechanism is employed to reduce the required synchronization between the simulation threads, thereby further increasing simulation speed. The virtual prototype of the European FP7 project EURETILE system simulator is used as demonstrator for the proposed work, showing a speedup of 4.01x on a four core host system compared to sequential simulation. |
| 16:03 | IP3-20, 128 | A UNIFIED METHODOLOGY FOR A FAST BENCHMARKING OF PARALLEL ARCHITECTURE Speakers: Alexandre Guerre, Jean-Thomas Acquaviva and Yves Lhuillier, CEA LIST, FR Abstract Benchmarking of architectures is today jeopardized by the explosion of parallel architectures and the dispersion of parallel programming models. Parallel programming requires architecture dependent compilers and languages as well as high programmer expertise. Thus, an objective comparison has become a harder task. This paper presents a novel methodology to evaluate and to compare parallel architectures in order to ease the programmer work. It is based on the usage of micro-benchmarks, code profiling and characterization tools. The main contribution of this methdology is a semi-automatic prediction of the performance for sequential applications on a set of parallel architectures. In addition the performance estimation is correlated with the cost of other criteria such as power or portability. Our methodology prediction was validated on anindustrial application. Results are within a range of 20%. |
| 16:00 | End of session Coffee Break in Exhibition Area On Tuesday-Thursday the coffee and lunch breaks will be located in the Exhibition Area (Terrace Level). |