Date: Wednesday 26 March 2014
Time: 14:30 - 16:00
Location / Room: Konferenz 3
Chair:
Aida Todri, CNRS, FR
Co-Chair:
Lars Bauer, KIT, DE
The papers in this sessions consider ways to improve the energy, performance, and reliability of emerging memory technologies. STT-RAM and PCRAM are addressed.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 14:30 | 7.5.1 | ASYNCHRONOUS ASYMMETRICAL WRITE TERMINATION (AAWT) FOR A LOW POWER STT-MRAM Speakers: Rajendra Bishnoi1, Mojtaba Ebrahimi2, Fabian Oboril2 and Mehdi Tahoori2 1Karlsruhe Institiute of Technology, DE; 2Karlsruhe Institute of Technology, DE Abstract Spin Transfer Torque (STT) memory is an emerging and promising non-volatile storage technology. However, the high write current is still a major challenge which leads to a huge power consumption of the memory. Due to an inherent torque asymmetry of the Magnetic Tunnel Junction (MTJ) device employed in STT memories, the switching time between parallel to anti-parallel and anti-parallel to parallel magnetization is significantly different. Hence, the write latencies for writing '0' and '1' are also considerably different. In this paper, we propose a technique called Asynchronous Asymmetrical Write Termination (AAWT) which utilizes this asymmetrical behavior to terminate the write operations asynchronously and as a result significantly reduces the write power consumption. Furthermore, we present two different AAWT implementations to determine the actual write termination times. The first one makes use of a clock signal and the second one employs a self-timing approach based on an internal delay element. As shown by our experimental results, AAWT can reduce the total write energy by 30 % in average with a negligible area overhead. |
| 15:00 | 7.5.2 | WRITE-ONCE-MEMORY-CODE PHASE CHANGE MEMORY Speakers: Jiayin Li and Kartik Mohanram, University of Pittsburgh, US Abstract This paper describes a write-once-memory-code phase change memory (WOM-code PCM) architecture for next-generation non-volatile memory applications. Specifically, we address the long latency of the write operation in PCM -- attributed to PCM SET -- by proposing a novel PCM memory architecture that integrates WOM-codes at the memory organization and memory controller levels. The proposed <2^2>^2/3 WOM-code PCM architecture is able to reduce memory write (read) latency by 20.1% (10.2%) on average across general-purpose (SPEC CPU2006), embedded (MiBench), and high-performance (SPLASH-2) benchmarks. To further improve the write latency of WOM-code PCM, we propose a PCM-refresh approach that uses idle cycles to preemptively set PCM rows to the initial WOM-code state. Results show that WOM-code PCM with PCM-refresh can reduce memory write (read) latency by 54.9% (47.9%) on average across the benchmarks. Finally, to balance write latency improvements against WOM-code PCM overhead, we propose a WOM-code cached PCM (WCPCM) architecture that uses WOM-code PCM as the cache alongside conventional PCM main memory. For just 4.7% memory overhead, WCPCM reduces memory write (read) latency by 47.2% (44.0%) on average across the benchmarks. |
| 15:30 | 7.5.3 | IMPROVING STT-MRAM DENSITY THROUGH MULTI-BIT ERROR CORRECTION Speakers: Brandon Del Bel, Jongyeon Kim, Chris H. Kim and Sachin S. Sapatnekar, University of Minnesota, US Abstract STT-MRAMs are prone to data corruption due to inadvertent bit flips. Traditional methods enhance robustness at the cost of area/energy by using larger cell sizes to improve the thermal stability of the MTJ cells. This paper employs multi-bit error correction with DRAM-style refreshing to mitigate errors and provides a methodology for determining the optimal level of correction. A detailed analysis demonstrates that the reduction in non-volatility requirements afforded by strong error correction translates to significantly lower area for the memory array compared to simpler ECC schemes, even when accounting for the increased overhead of error correction. |
| 16:00 | IP3-14, 458 | ENERGY EFFICIENT IN-MEMORY AES ENCRYPTION BASED ON NONVOLATILE DOMAIN-WALL NANOWIRE Speakers: Yuhao Wang1, Pingfan Kong1, Hao Yu1 and Dennis Sylvester2 1Nanyang Technological University, SG; 2University of Michigan, US Abstract The widely applied Advanced Encryption Standard (AES) encryption algorithm is critical in secure big-data storage. Data oriented applications have imposed high throughput and low power, i.e., energy efficiency (J/bit), requirements when applying AES encryption. This paper explores an in-memory AES encryption using the newly introduced domain-wall nanowire. We show that all AES operations can be fully mapped to a logic-in-memory architecture by non-volatile domain-wall nanowire, called DW-AES. The experimental results show that DW-AES can achieve the best energy efficiency of 24 pJ/bit, which is 9X and 6.5X times better than CMOS ASIC and ReRAM-CMOL implementations, respectively. Under the same area budget, the proposed DW-AES exhibits 6.4X higher throughput and 29\% power saving compared to a CMOS ASIC implementation; 1.7X higher throughput and 74\% power reduction compared to a ReRAM-CMOL implementation. |
| 16:01 | IP3-15, 391 | ICE: INLINE CALIBRATION FOR MEMRISTOR CROSSBAR-BASED COMPUTING ENGINE Speakers: Boxun Li1, Yu Wang1, Yiran Chen2, Helen Li2 and Huazhong Yang1 1Tsinghua University, CN; 2University of Pittsburgh, US Abstract The emerging neuromorphic computation provides a revolutionary solution to the alternative computing architecture and effectively extends Moore's Law. The discovery of the memristor presents a promising hardware realization of neuromorphic systems with incredible power efficiency, allowing efficiently executing the analog matrix-vector multiplication on the memristor crossbar architecture. However, during computations, the memristor will slowly drift from its initial programmed state, leading to a gradual decline of the computation precision of memristor crossbar-based computing engine (MCE). In this paper, we propose an inline calibration mechanism to guarantee the computation quality of the MCE. The inline calibration mechanism collects the MCE's computation error through `interrupt-and-benchmark (I&B)' operations and predicts the best calibration time through polynomial fitting of the computation error data. We also develop an adaptive technique to adjust the time interval between two neighbor I&B operations and minimize the negative impact of the I&B operation on system performance. The experiment results demonstrate that the proposed inline calibration mechanism achieves a calibration efficiency of 91.18% on average and negligible performance overhead (i.e., 0.439%) |
| 16:02 | IP3-16, 533 | COMPLEMENTARY RESISTIVE SWITCH BASED STATEFUL LOGIC OPERATIONS USING MATERIAL IMPLICATION Speakers: Yuanfan Yang1, Jimson Mathew1, Dhiraj K Pradhan1, Marco Ottavi2 and Salvatore Pontarelli2 1University of Bristol, GB; 2University of Rome "Tor Vergata", IT Abstract Memristor based logic and memories are increasingly becoming one of the fundamental building blocks for future system design. Hence, it is important to explore various methodologies for implementing these blocks. In this paper, we present a novel Complementary Resistive Switching (CRS) based stateful logic operations using material implication. The proposed solution benefits from exponential reduction in sneak path current in crossbar implemented logic. We validated the effectiveness of our solution through SPICE simulations on a number of logic circuits. It has been shown that only 4 steps are required for implementing N input NAND gate whereas memristor based stateful logic needs N+1 steps. |
| 16:00 | End of session Coffee Break in Exhibition Area On Tuesday-Thursday the coffee and lunch breaks will be located in the Exhibition Area (Terrace Level). |