Date: Wednesday 26 March 2014
Time: 11:00 - 12:30
Location / Room: Konferenz 2
Chair:
Edith Beigné, CEA LETI Grenoble, FR
Co-Chair:
Domenik Helms, OFFIS Oldenburg, DE
This session will present innovative solutions for power delivery in complex SoCs using configurable structures working over large condition range. Configurable DC-DC and LDOs architectures will be considered underlining power efficiency issues of off-chip and on-chip regulators. Fine-grain approaches are also proposed to deal with distributed in-die power generation reducing static and dynamic power in complex SoCs.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 11:00 | 6.4.1 | DESIGN AND EVALUATION OF FINE-GRAINED POWER-GATING FOR EMBEDDED MICROPROCESSORS Speakers: Masaaki Kondo1, Hiroaki Kobyashi2, Ryuichi Sakamoto2, Motoki Wada2, Jun Tsukamoto2, Mitaro Namiki2, Weihan Wang3, Hideharu Amano3, Kensaku Matsunaga4, Masaru Kudo4, Kimiyoshi Usami4, Toshiya Komoda5 and Hiroshi Nakamura5 1The University of Electro-Communications, JP; 2Tokyo University of Agriculture and Technology, JP; 3Keio University, JP; 4Shibaura Institute of Technology, JP; 5The University of Tokyo, JP Abstract Power-performance efficiency is still remaining a primary concern for microprocessor designers. One of the sources of power inefficiency for recent LSI chips is increasing leakage power consumption. Power-gating is a well known technique to reduce leakage power consumption by switching off the power supply to idle logic blocks. Recently, fine-grained power-gating is emerged as a technique to minimize leakage current during the active processor cycles by switching on and off a logic blocks in much finer temporal/spatial granularity. Though fine-grained power-gating is useful, a comprehensive evaluation and analysis has not been conducted on a real LSI chips. In this paper, we evaluate fine-grained run-time power-gating for microprocessors' functional units using a real embedded microprocessor. We also introduce an architecture and compiler co-operative power-gating scheme which mitigates negative power reduction caused by the energy overhead associated with fine-grained power-gating. The experimental results with a fabricated core shows that a hardware-based scheme saves power consumption of functional units by 44% and hardware compiler co-operative scheme further improves power efficiency by 5.9% when core temperature is 25C. |
| 11:30 | 6.4.2 | SUPERRANGE: WIDE OPERATIONAL RANGE POWER DELIVERY DESIGN FOR BOTH STV AND NTV COMPUTING Speakers: Xin He1, Guihai Yan2, Yinhe Han3 and Xiaowei Li3 1Institue of Computing Technology, Chinese Academy of Sciences; University of Chinese Academy of Sciences, CN; 2Institute of Computing Technology, Chinese Academy of Sciences, CN; 3institute of Computing Technology, Chinese Academy of Sciences, CN Abstract The load power range of modern processors is greatly enlarged because many advanced power management techniques like dynamic voltage frequency scaling, Turbo boosting, and Near Threshold Voltage technologies are incorporated. However, the power saving may be offset by power loss in power delivery; moreover, as the efficiency of power delivery varies greatly with different load conditions, conventional power delivery designs cannot maintain high efficiency over the entire voltage range. We propose SuperRange, a wide operational range power delivery scheme. SuperRange complements the power delivery capability of on-chip voltage regulator and off-chip voltage regulator. Experimental results show SuperRange has an average 70% power conversion efficiency over wide operational range which outperforms conventional power delivery schemes. And it also exhibits superior resilience to power-constrained systems. |
| 12:00 | 6.4.3 | MODELING AND ANALYSIS OF DIGITAL LDOS WITH ADAPTIVE CONTROL FOR HIGH EFFICIENCY UNDER WIDE DYNAMIC RANGE DIGITAL LOADS Speakers: Samantak Gangopadhyay, Youngtak Lee, Saad Bin Nasir and Arijit Raychowdhury, Georgia Institute of Technology, US Abstract Discrete time digital linear regulators, including low dropout regulators (LDOs) have become competitive in muti-Vcc digital systems for fine-grained spatio-temporal voltage regulation and distribution. However wide dynamic current range of the digital load circuits poses serious problems in maintaining stability and high efficiency at all corners. In this paper we present a control model for discrete time LDOs and demonstrate how online adaptive control can be employed for consistent performance and high efficiency across the load current range. |
| 12:30 | End of session Lunch Break in Exhibition Area Sandwich lunch |