Date: Wednesday 26 March 2014
Time: 11:00 - 12:30
Location / Room: Konferenz 6
Organisers:
Michael Niemier, University of Notre Dame, US
X. Sharon Hu, University of Notre Dame, US
Chair:
Michael Niemier, University of Notre Dame, US
This "vertically integrated" session is focused on emerging transistor technologies - particularly devices that operate at low voltages and that have steep slopes. It will: (1) introduce desirable (and undesirable) features of new device technologies; (2) highlight how new transistor technologies could impact von Neumann architectures; a particular emphasis will be placed on (a) heterogeneous multi-core architectures and accelerators (where heterogeneity stems from different device technologies) and (b) modeling efforts at all levels of the chip hierarchy (i.e., from the device-level to the architectural-level); (3) illustrate how new device technologies could lead to significant improvements in the performance/efficiency of non-von Neumann architectures. Notably, talks (2) and (3) will identify roles for new device technologies in hybrid analog-digital systems with an end goal of improved application-level performance/efficiency.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 11:00 | 6.2.1 | ENERGY EFFICIENT COMPUTING WITH TUNNEL FETS Speakers: Adrian Ionescu, Arnab Biswas, Nilay Dagtekin and Livio Lattanzio, Nanolab, Ecole Polytechnique Fédérale de Lausanne, CH Abstract This paper will review the state-of-the-art in energy efficient computing using tunnel FETs from device to circuit level, including digital IC and memory applications. At device level we will particularly discuss the major challenges remaining for tunnel FETs, with particular emphasis on: (i) selection of the most appropriate material systems and band-gap engineering of heterostructure Tunnel FETs to simultaneously offer best performance trade-off: low Ioff, high Ion, high Ion/Ioff, subthermal swing over more than 4 decades of current, and operation below 0.3V, (ii) specifically optimized device design (i.e. field aligned to the tunneling path, avoidance of super-linear onset, minimize Miller effect), (iii) understanding the role of defects for BTBT and providing appropriate control, (iv) understanding and controlling parameter sensitivity and variability, (v) accurate physics-based BTBT modeling of heterojunction tunnel FETs. We will detail the Electron-Hole Bilayer Tunnel FET (EHBTFET), as switch candidate for sub-0.1V operation exploiting tunneling through a bias-induced electron-hole bilayer based on a calibrated quantum-mechanical simulator. We will make performance projections for EHBTFET complementary logic compared to CMOS logic of same dimensions and using recent energy benchmarking. Finally, the design and use of Tunnel FETs as capacitorless DRAM cells, implemented as a double-gate (DG) fully-depleted Silicon-On-Insulator (FD-SOI) architecture will be reported and its principle, embodiment and scalability discussed. We will present recent experimental results on Tunnel FET DRAM memory operation schemes and demonstrate its potential for ultra-low power memories. In conclusion, this paper demonstrates that Tunnel FETs stand as the most promising steep slope switch candidates to reduce the supply voltage below 0.3 V and offer significant power dissipation savings for digital computing. |
| 11:30 | 6.2.2 | MODELING STEEP SLOPE DEVICES: FROM CIRCUITS TO ARCHITECTURES Speakers: Karthik Swaminathan1, Moon Seok Kim1, Nandhini Chandramoorthy2, Behnam Sedighi3, Robert Perricone3, Jack Sampson1 and Vijaykrishnan Narayanan4 1Pennsylvania State University, US; 2The Pennsylvania State University, US; 3University of Notre Dame, US; 4Penn State University, US Abstract Steep Slope devices, with Heterojunction Tunnel FETs (TFETs) in particular, have been proposed as a viable solution to overcome the subthreshold slope limitation in exist- ing CMOS technology and achieve ultra-low voltage operation with acceptable performance. However, state-of-the-art FinFET technologies continue to demonstrate superior performance than steep slope devices in application domains demanding peak single threaded performance. In this context, we examine different computing paradigms where TFET technologies can be used, not just as a 'drop in' replacement, but as an additional parameter to augment the architectural design space. This greatly widens the scope of optimizations for performance and power. We investigate the tradeoffs between device and architectures in general purpose processors when performance, power and temperature are individually constrained. We also synthesize examples of domain-specific accelerators used in computer vision using in-house TFET standard cell libraries to demonstrate the energy benefits of designing TFET-based accelerators. We demonstrate that synthesizing these accelerators using TFETs reduces energy by over 6X in comparison to an equivalent iso- voltage CMOS-based design and by over 30% in comparison to an iso-performance CMOS design. |
| 12:00 | 6.2.3 | STEEP SLOPE TRANSISTOR TECHNOLOGIES: IMPACTS ON CNN ARCHITECTURES Speakers: Indranil Palit1, Behnam Sedighi1, Xiaobo Sharon Hu1, Joseph Nahas1, Michael Niemier1 and András Hortváth2 1University of Notre Dame, US; 2Pázmány Péter Catholic University, HU Abstract A Cellular Neural Network (CNN) is a highly-parallel, analog processor that can significantly outperform von Neumann architectures for certain classes of problems. In this paper, we illustrate how emerging, beyond-CMOS devices could help to further enhance the capabilities of CNNs, particularly for solving problems with non-binary outputs. We show how CNNs based on devices such as graphene transistors - with multiple steep current growth regions separated by negative differential regions (NDR) in their I-V characteristics - could be used to recognize multiple patterns simultaneously. (This would require multiple steps given a conventional, binary CNN.) Also, we demonstrate how circuits based on tunneling field effect transistors (TFETs) can also be used to form circuits capable of performing similar tasks. With this approach, more "exotic" I-V characteristics are not required - which should be an asset when considering issues such as cell-to-cell mismatch, etc. As a case study, we present a CNN-cell design that employs TFET-based circuitry to realize ternary outputs. We then illustrate how this hardware could be employed to efficiently solve a tactile sensing problem. The total number of computation steps, as well as the required hardware could be reduced significantly when compared to an approach based on a conventional CNN. |
| 12:30 | End of session Lunch Break in Exhibition Area Sandwich lunch |