Date: Wednesday 26 March 2014
Time: 08:30 - 10:00
Location / Room: Konferenz 4
Chair:
Mehdi Tahoori, KIT, DE
Co-Chair:
Marco Ottavi, University of Rome "Tor Vergata", IT
The papers in this session consider new ways to realize both Boolean and non-Boolean logic. Potential implementations are based on graphene, spin, and resonance energy transfer.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 08:30 | 5.6.1 | RETLAB: A FAST DESIGN-AUTOMATION FRAMEWORK FOR ARBITRARY RET NETWORKS Speakers: Mohammad Mottaghi, Arjun Rallapalli and Chris Dwyer, Duke University, US Abstract Resonance energy transfer (RET) circuits are networks of photo-active molecules that can implement arbitrary logic functions. The nanoscale size of these structures can bring high-density computation to new domains, e.g., in vivo sensing and computation. A key challenge in the design of a RET network is to find, among a huge set of configurations (i.e., design space), the optimum choice and arrangement of molecules on a nanostructure. The prohibitively large size of the design space makes it impractical to evaluate every possible configuration, motivating the need for design-space pruning to be integrated into the design flow. To this end, we have developed a computer-aided design framework, called RETLab, that enables structured pruning of the design space to extract a sufficiently small subset, which is fully evaluated and ranked based on user-defined metrics to yield the best configuration. More importantly, we have developed a new RET-simulation algorithm, which is several orders of magnitude (e.g., for a 4-node network, one million times) faster than the conventional Monte-Carlo-based simulation (MCS). This speedup in configuration evaluation enables a significantly more extensive design-space exploration with fewer and less constrained heuristics, compared to existing RET-network design methods which are ad-hoc and rely on MCS for configuration evaluation. |
| 09:00 | 5.6.2 | DESIGN OF 3D NANOMAGNETIC LOGIC CIRCUITS: A FULL-ADDER CASE STUDY Speakers: Robert Perricone, X. Sharon Hu, Joe Nahas and Michael Niemier, University of Notre Dame, US Abstract Nanomagnetic logic (NML) is a ``beyond-CMOS'' technology that combines logic and memory capabilities through field-coupled interactions between nanoscale magnets. NML is intrinsically non-volatile, low-power, and radiation-hard when compared to CMOS equivalents. Moreover, there have been numerous demonstrations of NML circuit functionality within the last decade. These fabricated structures typically employ devices with in-plane magnetization to move and process data. However, in-plane layouts imply circuits and interconnects in only two dimensions (2D), which makes signal routing -- and hence circuits -- more complex. In this paper, we introduce NML circuits that move and process data in three dimensions (3D). We employ devices with perpendicular magnetic anisotropy (PMA) (i.e., out-of-plane magnetization states) and discuss their behavior when utilized in 3D designs. Furthermore, we provide a systematic design approach for 3D NML circuits using a threshold full adder as a case study. We compare our 3D adder to 2D adders to highlight the benefits of 3D NML circuits, which include simpler signal routing and a smaller area footprint. |
| 09:30 | 5.6.3 | HIGHLY ACCURATE SPICE-COMPATIBLE MODELING FOR SINGLE- AND DOUBLE-GATE GNRFETS WITH STUDIES ON TECHNOLOGY SCALING Speakers: Morteza Gholipour1, Ying-Yu Chen2, Amit Sangai2 and Deming Chen2 1University of Tehran, IR; 2University of Illinois at Urbana-Champaign, US Abstract In this paper, we present a highly accurate closed-form compact model for Schottky-Barrier-type Graphene Nano-Ribbon Field-Effect Transistors (SB-GNRFETs). This is a physics-based analytical model for the current-voltage (I-V) characteristics of SB-GNRFETs. We carry out accurate approximations of Schottky barrier tunneling, channel charge and current, which provide improved accuracy while maintaining compactness. This SPICE-compatible compact model surpasses the existing model [15] in accuracy, and enables efficient circuit-level simulations of futuristic GNRFET-based circuits. The proposed model considers various design parameters and process variation effects, including graphene-specific edge roughness, which allows complete and thorough exploration and evaluation of SB-GNRFET circuits. We are able to model both single- and double-gate SB-GNRFETs, so we can evaluate and compare these two types of SB-GNRFET. We also compare circuit-level performance of SB-GNRFETs with multi-gate (MG) Si-CMOS for a scalability study in future generation technology. Our circuit simulations indicate that SB-GNRFET has an energy-delay product (EDP) advantage over Si-CMOS; the EDP of the ideal SB-GNRFET (assuming no process variation) is ~1.3% of that of Si-CMOS, while the EDP of the non-ideal case with process variation is 136% of that of Si-CMOS. Finally, we study technology scaling with SB-GNRFET and MG Si-CMOS. We show that the EDP of ideal (non-ideal) SB-GNRFET is ~0.88% (54%) EDP of that of Si-CMOS as the technology nodes scales down to 7 nm. |
| 09:45 | 5.6.4 | REWIRING FOR THRESHOLD LOGIC CIRCUIT MINIMIZATION Speakers: Chia-Chun Lin1, Chun-Yao Wang1, Yung-Chih Chen2 and Ching-Yi Huang1 1Dept. of Computer Science, National Tsing Hua University, TW; 2Dept. of Computer Science and Engineering, Yuan Ze University, TW Abstract Recently, there have been many works focusing on synthesis, verification, and testing of threshold circuits due to the rapid development in efficient implementation of threshold logic circuits. To minimize the hardware cost of threshold circuit implementation, this paper proposes a heuristic that consists of rewiring operations and a simplification procedure. Additionally, a subset of input vectors of a gate, called critical-effect vectors, are proved to be complete for formally verifying the equivalence of two threshold logic gates, instead of the whole truth table in this paper. This achievement can accelerate the equivalence checking of two threshold logic gates. The experimental results show that the proposed heuristic can efficiently reduce the cost. |
| 10:00 | IP2-17, 238 | WIDTH MINIMIZATION IN THE SINGLE-ELECTRON TRANSISTOR ARRAY SYNTHESIS Speakers: Chian-Wei Liu1, Chang-En Chiang1, Ching-Yi Huang1, Chun-Yao Wang1, Yung-Chih Chen2, Suman Datta3 and Vijaykrishnan Narayanan4 1Dept. of Computer Science, National Tsing Hua University, TW; 2Dept. of Computer Science and Engineering, Yuan Ze University, TW; 3Department of Electrical Engineering, The Pennsylvania State University, US; 4Department of Computer Science and Engineering, The Pennsylvania State University, US Abstract Power consumption has become one of the primary challenges to meet the Moore's law. For reducing power consumption, Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultra-low power consumption during operation. Prior work has proposed an automated mapping approach for SET architecture which focuses on minimizing the number of hexagons in an SET array. However, the area of an SET array is more related to the width. Consequently, in this work, we propose an approach for width minimization of the SET arrays. The experimental results show that the proposed approach saves 26% of width compared with the state-of-the-art for a set of MCNC and IWLS 2005 benchmarks while spending similar CPU time. |
| 10:01 | IP2-18, 704 | AREA MINIMIZATION SYNTHESIS FOR RECONFIGURABLE SINGLE-ELECTRON TRANSISTOR ARRAYS WITH FABRICATION CONSTRAINTS Speakers: Yi-Hang Chen, Jian-Yu Chen and Juinn-Dar Huang, Department of Electronics Engineering, National Chiao Tung University, TW Abstract As fabrication processes exploit even deeper submicron technology, power dissipation has become a crucial issue for most electronic circuit and system designs nowadays. In particular, leakage power is becoming a dominant source of power consumption. Recently, the reconfigurable single-electron transistor (SET) array has been proposed as an emerging circuit design style for continuing Moore's Law due to its ultra-low power consumption. Several automated synthesis approaches have been developed for the reconfigurable SET array in the past few years. Nevertheless, all of those existing methods consider fabrication constraints, which are mandatory, merely in late synthesis stages. In this paper, we propose a synthesis algorithm, featuring both variable reordering and product term reordering, for area minimization. In addition, our algorithm takes those mandatory fabrication constraints into account in early stages for better outcomes. Experimental results show that our new method can achieve an area reduction of up to 24% as compared to current state-of-the-art techniques. |
| 10:02 | IP2-19, 247 | SOFTWARE-BASED PAULI TRACKING IN FAULT-TOLERANT QUANTUM CIRCUITS Speakers: Alexandru Paler1, Simon Devitt2, Kae Nemoto2 and Ilia Polian1 1University of Passau, DE; 2National Institute of Informatics, JP Abstract The realisation of large-scale quantum computing is no longer simply a hardware question. The rapid development of quantum technology has resulted in dozens of control and programming problems that should be directed towards the classical computer science and engineering community. One such problem is known as Pauli tracking. Methods for implementing quantum algorithms that are compatible with crucial error correction technology utilise extensive quantum teleportation protocols. These protocols are intrinsically probabilistic and result in correction operators that occur as byproducts of teleportation. These byproduct operators do not need to be corrected in the quantum hardware itself , but are tracked through the circuit and output results emph{reinterpreted}. This tracking is routinely ignored in quantum information as it is assumed that tracking algorithms will eventually be developed. In this work we help fill this gap and present an algorithm for tracking byproduct operators through a quantum computation. |
| 10:00 | End of session Coffee Break in Exhibition Area On Tuesday-Thursday the coffee and lunch breaks will be located in the Exhibition Area (Terrace Level). |