Date: Wednesday 26 March 2014
Time: 08:30 - 10:00
Location / Room: Konferenz 2
Chair:
Antonio Rubio, UPC Barcelona, ES
Co-Chair:
Marisa López Vallejo, UPM Madrid, ES
The session addresses yield analysis due to timing variations as well as various flip flop design techniques improving timing margins under variability.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 08:30 | 5.4.1 | EFFICIENT HIGH-SIGMA YIELD ANALYSIS FOR HIGH DIMENSIONAL PROBLEMS Speakers: Moning Zhang, Zuochang Ye and Yan Wang, Tsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University, CN Abstract High-sigma analysis is important for estimating the probability of rare events. Traditional high-sigma analysis can only work for small-size (low-dimension) problems limiting to 10 ~ 20 random variables, mostly due to the difficulty of finding optimal boundary points. In this paper we propose an efficient method to deal with high-dimension problems. The proposed method is based on performing optimization in a series of low dimension parameter spaces. The final solution can be regarded as a greedy version of the global optimization. Experiments show that the proposed method can efficiently work with problems with > 100 independent variables. |
| 09:00 | 5.4.2 | SUB-THRESHOLD LOGIC CIRCUIT DESIGN USING FEEDBACK EQUALIZATION Speakers: Mahmoud Zangeneh and Ajay Joshi, Boston University, US Abstract Low energy has become one of the primary constraint in the design of digital VLSI circuits in recent years. Minimum-energy consumption can be achieved in digital circuits by operating in the sub-threshold regime. However, in this regime process variation can result in up to an order of magnitude variations in Ion/Ioff ratios leading to timing errors, which can have a detrimental impact on the functionality of the sub-threshold circuits. These timing errors become more frequent in scaled technology nodes where process variations are highly prevalent. Therefore, mechanisms to mitigate these timing errors while minimizing the energy consumption in sub-threshold circuits are required. In this paper, we propose the use of a variable threshold feedback equalizer circuit with combinational logic blocks to mitigate the timing errors, which can then be leveraged to reduce the dominant leakage energy by scaling supply voltage or decreasing the propagation delay. At the fixed supply voltage, we can decrease the propagation delay of the critical path using equalizer circuits and, correspondingly decrease the leakage energy consumption. For a 8-bit carry lookahead adder designed in UMC 130 nm process, the operating frequency can be increased by 22.87% (on average), while reducing the leakage energy by 22.6% in the sub-threshold regime. Overall the feedback equalization technique provides up to 35.4% lower energy-delay product compared to the conventional non-equalized logic. Alternately, for a 8-bit carry lookahead adder, the proposed technique enables us to reduce the critical voltage (beyond which timing errors occur) from 300 mV (nominal design) to 270 mV (design with feedback circuit), and provides a 16.72% decrease in energy per operation while maintaining performance. |
| 09:30 | 5.4.3 | STOCHASTIC ANALYSIS OF BUBBLE RAZOR Speakers: Guowei Zhang1 and Peter Beerel2 1Tsinghua University, CN; 2Univ. of Southern California, US Abstract Bubble Razor has been proposed to eliminate required timing margins in synchronous design caused by increasing delay variation due to process variation and aging. However, the theoretical analysis of its performance under variability is unknown. This paper presents a Markov Chain model to describe the behavior of Bubble Razor. Using this model, we analyze its performance and provide an optimizing strategy to maximize its benefits |
| 10:00 | IP2-13, 1013 | (Best Paper Award Candidate) MINIMIZING STATE-OF-HEALTH DEGRADATION IN HYBRID ELECTRICAL ENERGY STORAGE SYSTEMS WITH ARBITRARY SOURCE AND LOAD PROFILES Speakers: Yanzhi Wang1, Xue Lin1, Qing Xie1, Naehyuck Chang2 and Massoud Pedram1 1University of Southern California, US; 2Seoul National University, KR Abstract Hybrid electrical energy storage (HEES) systems consisting of heterogeneous electrical energy storage (EES) elements are proposed to exploit the strengths of different EES elements and hide their weaknesses. The cycle life of the EES elements is one of the most important metrics. The cycle life is directly related to the state-of-health (SoH), which is defined as the ratio of full charge capacity of an aged EES element to its designed (or nominal) capacity. The SoH degradation models of battery in the previous literature can only be applied to charging/discharging cycles with the same state-of-charge (SoC) swing. To address this shortcoming, this paper derives a novel SoH degradation model of battery for charging/discharging cycles with arbitrary patterns. Based on the proposed model, this paper presents a near-optimal charge management policy focusing on extending the cycle life of battery elements in the HEES systems while simultaneously improving the overall cycle efficiency. |
| 10:01 | IP2-14, 517 | DYNAMIC FLIP-FLOP CONVERSION TO TOLERATE PROCESS VARIATION IN LOW POWER CIRCUITS Speakers: Mehrzad Nejat, Bijan Alizadeh and Ali Afzali Kusha, School of Electrical and Computer Eng., College of Eng., University of Tehran, IR Abstract A novel time borrowing method called dynamic Flip-Flop conversion is presented in this paper. A timing violation predictor detects the violations halfway in the critical path and dynamically converts the critical Flip-Flop to a latch. This way, time borrowing benefits of latches are utilized in a Flip-Flop based design which is more adaptable with Computer-Aided- Design tools. The overhead of this method is smaller than that of similar methods due to the elimination of delay elements. According to the post-synthesis simulations and Monte-Carlo analysis of Spice simulations on some ITC'99 benchmark circuits, the power overhead of the proposed method is about 15% and 19% smaller than that of Soft-Edge-Flip-Flop and Dynamic- Clock-Stretching circuits respectively in a simple case of about 40% yield improvement. This overhead would be relatively even smaller for higher performance and yield improvements. |
| 10:02 | IP2-15, 900 | A LOW POWER AND ROBUST CARBON NANOTUBE 6T SRAM DESIGN WITH METALLIC TOLERANCE Speakers: Luo Sun1, Jimson Mathew1, Rishad Shafik2, Dhiraj Pradhan1 and Zhen Li1 1University of Bristol, GB; 2University of Southampton, GB Abstract Carbon nanotube field-effect transistor (CNTFET) is envisioned as a promising device to overcome the limitations of traditional CMOS based MOSFETs due to its favourable physical properties. This paper presents a novel six-transistor (6T) static random access memory (SRAM) bitcell design using CNTFETs. Extensive validations and comparative analyses are carried out with the proposed SRAM design using SPICE based simulations. We show that the proposed CNTFET based SRAM has a significantly better static noise margin (SNM) and write ability margin (WAM) compared to a CNTFET-based standard 6T bitcell, equivalent to isolated read-port 8T cell based on CNTFET, while consuming less dynamic power. We further demonstrate that it exhibits higher robustness under process, voltage and temperature (PVT) variations when compared with the traditional CMOS SRAM cell designs. Furthermore, metallic CNTs removal technique is used considering metallic tolerance to make the proposed SRAM design more reliable. |
| 10:00 | End of session Coffee Break in Exhibition Area On Tuesday-Thursday the coffee and lunch breaks will be located in the Exhibition Area (Terrace Level). |