Date: Thursday 27 March 2014
Time: 16:00 - 17:30
Location / Room: Konferenz 5
Chair:
Jacob A. Abraham, University of Texas at Austin, US
Co-Chair:
Marian Verhelst, KU Leuven, BE
Presentations in this session offer solutions to equip mixed-signal and RF circuits with built-in self-test capabilities. These solutions include the use of an on-chip neural network that maps test signatures directly to a pass/fail decision, loopback test where the transmitter is used to test the receiver, and a reconfiguration principle for pipelined data converters.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 16:00 | 12.7.1 | (Best Paper Award Candidate) AN ANALOG NON-VOLATILE NEURAL NETWORK PLATFORM FOR PROTOTYPING RF BIST SOLUTIONS Speakers: Dzmitry Maliuk1 and Yiorgos Makris2 1Yale University, US; 2University of Texas at Dallas, US Abstract We introduce an analog non-volatile neural network chip which serves as an experimentation platform for prototyping custom classifiers for on-chip integration towards fully stand-alone built-in self-test (BIST) solutions for RF circuits. Our chip consists of a reconfigurable array of synapses and neurons operating below threshold and featuring sub-μW power consumption. The synapse circuits employ dynamic weight storage for fast bidirectional weight updates during training. The learned weights are then copied onto analog floating gate (FG) memory for permanent storage. The chip architecture supports two learning models: a multilayer perceptron and an ontogenic neural network. A benchmark XOR task is first employed to evaluate the overall learning capability of our chip. The BIST-related effectiveness is then evaluated on two case studies: the detection of parametric and catastrophic faults in an LNA and an RF front-end circuits, respectively. |
| 16:30 | 12.7.2 | BUILT-IN SELF-TEST AND CHARACTERIZATION OF POLAR TRANSMITTER PARAMETERS IN THE LOOP-BACK MODE Speakers: Jae Woong Jeong1, Sule Ozev1, Shreyas Sen2, Vishwanath Natarajan2 and Mustapha Slamani3 1Arizona State University, US; 2Intel Corporation, US; 3IBM Corp., US Abstract This paper presents a Built-in-self-test (BIST) solution for polar transmitters with low cost. Polar transmitters are desirable for portable devices due to higher power efficiency they provide compared to traditional Cartesian transmitters. However, they generally require iterative test/measurement/calibration cycles. The delay skew between the envelope and phase signals and the finite envelope bandwidth can create inter modulation distortion (IMD) that leads to the violation of the spectral mask and error vector magnitude (EVM) requirements. These parameters are typically not directly measured but calibrated through spectral performance analysis using expensive RF equipment, leading to lengthy and costly measurement/calibration cycles. Characterization and calibration of these parameters inside the device would reduce the test time and cost considerably. In this paper, we propose a technique to measure the delay skew and the finite envelope bandwidth, two parameters that can be digitally calibrated, based on the measurement of the output of the receiver in the loop-back mode. Simulation and hardware measurement results show that the proposed technique can characterize the targeted impairments in the polar transmitter accurately. |
| 17:00 | 12.7.3 | A FLEXIBLE BIST STRATEGY FOR SDR TRANSMITTERS Speakers: Emanuel Dogaru1, Filipe Vinci dos Santos2 and William Rebernak1 1Thales Communications & Security, FR; 2Thales Chair on Advanced Analog Design, SUPELEC, FR Abstract Software-defined radio (SDR) development aims for increased speed and flexibility. The impact of these system-level requirements on the physical layer (PHY) access hardware is leading to more complex architectures, which together with higher levels of integration pose a challenging problem for product testing. For radio units that must be field-upgradeable without specialized equipment, Built-in Self-Test (BIST) schemes are arguably the only way to ensure continued compliance to specifications. In this paper we introduce a loopback RF BIST technique that uses Periodically Nonuniform Sampling (PNS2) of the transmitter (TX) output to evaluate compliance to spectral mask specifications. No significant hardware costs are incurred due to the re-use of available RX resources (I/Q ADCs, DSP, GPP, etc.). Simulation results of an homodyne TX demonstrate that Adjacent Channel Power Ratio (ACPR) can be accurately estimated. Future work will consist in validating our loopback RF BIST architecture on an in-house SDR testbed. |
| 17:15 | 12.7.4 | SIGMA-DELTA TESTABILITY FOR PIPELINE A/D CONVERTERS Speakers: Antonio Jose Gines Arteaga and Gildas Leger, Instituto de Microelectronica de Sevilla, IMSE-CNM, (CSIC - Universidad de Sevilla), ES Abstract Pipeline Analog to Digital Converters (ADCs) are widely used in applications that require medium to high resolution at high acquisition speed. Despite of their quite simple working principles, they usually form rather complex mixed-signal blocks, particularly if digital correction and calibration are considered. As a result, pipeline converters are difficult to test and diagnose. In this paper, we propose to reconfigure the internal Multiplying DACs (MDACs) that perform residue amplifications as integrators, each one with an analog and a digital input. In this way, we can reuse consecutive pipeline stages to form Sigma Delta modulators, with very reduced area overhead. We thus get an on-chip DC (low-frequency) probe with a digital 1-bit output that does not require any extra pin. In addition, digital test techniques developed for Sigma Delta modulators may be used to enhance the diagnosing capabilities. An industrial 1.8V 15-bit 100Msps pipeline ADC that had previously been fully validated in a 0.18um CMOS process is used as a case of study for the introduction of the DfT modifications. |
| 17:30 | End of session | |