Date: Thursday 27 March 2014
Time: 16:00 - 17:30
Location / Room: Konferenz 4
Chair:
William Fornaciari, Politecnico di Milano - DEIB, IT
Co-Chair:
Kim Gruettner, OFFIS, DE
This session addresses the trade-off between accuracy and power consumption and the management of multi core/multi systems. The power management is addressed at several abstraction levels from circuit and performance counters up to the system level (operating system).
| Time | Label | Presentation Title Authors |
|---|---|---|
| 16:00 | 12.6.1 | ASLAN: SYNTHESIS OF APPROXIMATE SEQUENTIAL CIRCUITS Speakers: Ashish Ranjan, Arnab Raha, Swagath Venkataramani, Kaushik Roy and Anand Raghunathan, PURDUE UNIVERSITY, US Abstract Applications from several important domains exhibit intrinsic resilience to approximations or inexactness in their underlying computations. Approximate circuits are commonly used to realize highly efficient hardware implementations of such applications. A wide range of manual and automatic techniques for the design of approximate circuits have been proposed. However, all of them target combinational circuits, leaving a gap between these techniques and the natural granularity at which quality is specified. In practice, the designer is concerned with quality or accuracy at the output of a sequential circuit after several cycles of computation, and not at the output of an embedded combinational block. We propose ASLAN (Automatic methodology for Sequential Logic ApproximatioN), the first effort towards the synthesis of approximate sequential circuits. Given an RTL or gate-level description of a sequential circuit and a quality constraint at its output, ASLAN automatically synthesizes an approximate version that guarantees the specified quality bound. The key challenges in approximating sequential circuits are (i) to model how errors due to approximations are generated, propagate through multiple cycles of operation, and eventually impact quality of the final output, and (ii) to select the most beneficial approximations, i.e., those that result in higher energy savings for smaller impact on output quality. We address the first challenge by constructing a virtual Sequential Quality Constraint Circuit (SQCC) and utilizing formal verification to ensure that a given approximation satisfies the quality constraint during synthesis. To address the second challenge, we identify combinational blocks in the sequential circuit that are amenable to approximation, generate local quality-energy trade-off curves for them, and use a gradient-descent approach to iteratively approximate the sequential circuit. We used ASLAN to automatically synthesize approximate versions for several sequential benchmarks (DCT, FIR, IIR, etc.). Our experiments demonstrate energy reductions of 1.20X-2.44X for tight error constraints, and 1.32X-4.42X for relaxed error constraints. We also present case studies of using the approximate circuits generated by ASLAN in two well known applications — MPEG Encoding and K-Means Clustering. We obtain energy savings of 1.32X with 0.5% average degradation in PSNR for the MPEG Encoder and 1.26X with 0.8% quality loss in case of KMeans Clustering. |
| 16:30 | 12.6.2 | VRCON: DYNAMIC RECONFIGURATION OF VOLTAGE REGULATORS IN A MULTICORE PLATFORM Speakers: Woojoo Lee, Yanzhi Wang and Massoud Pedram, University of southern california, US Abstract The emerging trend toward utilizing chip multi-core processors (CMPs) that support dynamic voltage and frequency scaling (DVFS) is driven by user requirements for high performance and low power. To overcome limitations of the conventional chip-wide DVFS and achieve the maximum possible energy saving, per-core DVFS is being enabled in the recent CMP offerings. While power consumed by the CMP is reduced by per-core DVFS, power dissipated by many voltage regulators (VRs) needed to support per-core DVFS becomes critical. This paper focuses on the dynamic control of the VRs in a CMP platform. Starting with a proposed platform with a configurable VR-to-core power distribution network, two optimization methods are presented to maximize the system-wide energy savings: (i) reactive VR consolidation to reconfigure the network for maximizing the power conversion efficiency of the VRs performed under the pre-determined DVFS levels for the cores, and (ii) proactive VR consolidation to determine new DVFS levels for maximizing the total energy savings without any performance degradation. Results from detailed experiments demonstrate up to 35% VR energy loss reduction and 14% total energy saving. |
| 17:00 | 12.6.3 | COARSE-GRAINED BUBBLE RAZOR TO EXPLOIT THE POTENTIAL OF TWO-PHASE TRANSPARENT LATCH DESIGNS Speakers: Hayoung Kim, Jae-joon Kim, Sungjoo Yoo, Sunggu Lee and Dongyoung Kim, POSTECH, KR Abstract Timing margin to cover process variation is one of the most critical factors that limit the amount of supply voltage reduction thereby power consumption. To remove too conservative timing margin, Bubble Razor was introduced to dynamically detect and correct errors in two-phase transparent latch designs [13]. However, it does not fully exploit the potential of two-phase transparent latch design, e.g. time borrowing. Thus, especially at low supply voltage where the effect of process variation becomes significant, the existing Bubble Razor can suffer from significant overhead in performance and power consumption due to too frequent occurrence of bubble generations. We present a design methodology for coarse-grained Bubble which exploits the time-borrowing characteristic of two-phase transparent latch design. By selectively inserting error checkpoints, i.e., shadow latches and error management logic, in the circuit, time borrowing can be applied between error checkpoints thereby avoiding bubbles which could occur in the existing Bubble Razor design with a checkpoint at every latch on the critical path. We present a methodology to choose the grain size (the number of stages between error checkpoints) based on 3-sigma delay distribution. We also verify the benefits of coarse-grained Bubble Razor with a real microprocessor, Core-A design [15] using 20nm Predictive Technology Model (PTM) [16]. The proposed methodology offers 62% improvement in performance (MIPS) and 49% less energy consumption (per instruction) at 0.6V operation (zero frequency margin) over the original Bubble Razor scheme. In addition, it gives 25% area reduction in core design. |
| 17:15 | 12.6.4 | FEPMA: FINE-GRAINED EVENT-DRIVEN POWER METER FOR ANDROID SMARTPHONES BASED ON DEVICE DRIVER LAYER EVENT MONITORING Speakers: Kitae Kim1, Donghwa Shin2, Qing Xie3, Yanzhi Wang3, Massoud Pedram3 and Naehyuck Chang1 1Seoul National University, KR; 2Politecnico di Torino, IT; 3University of Southern California, US Abstract This paper introduces a novel sensor-less, event-driven power analysis framework called FEPMA for providing highly accurate and nearly instantaneous estimates of power dissipation in an Android smartphone. The key idea is to collect and correctly record various events of interest within a smartphone as applications are running on the application processor within it. This is in turn done by instrumenting the Android operating system to provide information about power/performance state changes of various smartphone components at the lowest layer of the kernel to avoid time stamping delays and component state observability issues. This technique then enables one to perform fine-grained (in time and space) power metering in the smartphone. Experimental results show significant accuracy improvement compared to previous approaches and good fidelity with respect to actual current measurements. The estimation error of the proposed method is lower by a factor of two than the state-of-the-art method. |
| 17:30 | End of session | |