Date: Thursday 27 March 2014
Time: 16:00 - 17:30
Location / Room: Konferenz 1
Chair:
Theocharides Theocharis, University of Cyprus, CY
Co-Chair:
Cristiana Bolchini, Politecnico di Milano, IT
The session presents designs for energy efficient and flexible implementations of advanced video coders or image acquisition/processing systems
| Time | Label | Presentation Title Authors |
|---|---|---|
| 16:00 | 12.3.1 | FLEXIBLE AND SCALABLE IMPLEMENTATION OF H.264/AVC ENCODER FOR MULTIPLE RESOLUTIONS USING ASIPS Speakers: Hong Chinh Doan, Haris Javaid and Sri Parameswaran, School of Computer Science and Engineering, University of New South Wales, Sydney, Australia, AU Abstract Real-time encoding of video streams is computationally intensive and rarely carried out at high resolutions. In this paper, for the first time, we propose a platform for H.264 encoder which is both flexible (allows software upgrades) and scalable (supports multiple resolutions), and supports high video quality (by using both intraprediction and interprediction) and high throughput (by exploiting slice-level and pixel-level parallelisms). Our platform uses multiple Application Specific Instruction set Processors (ASIPs) with local and shared memories, and hardware accelerators (in the form of custom instructions). Our platform can be configured to use a particular number of ASIPs (slices per video frame) for a specific video resolution at design-time. The MPSoC architecture is automatically generated by our platform and the H.264 software does not need any modification, which enables quick design space exploration. We implemented the proposed platform in a commercial design environment, and illustrated its utility by creating systems with up to 170 ASIPs supporting resolutions up to HD1080. We further show how power gating can be used in our platform to save energy consumption. |
| 16:30 | 12.3.2 | A FLEXIBLE ASIP ARCHITECTURE FOR CONNECTED COMPONENTS LABELING IN EMBEDDED VISION APPLICATIONS Speakers: Juan Fernando Eusse1, Rainer Leupers1, Gerd Ascheid1, Patrick Sudowe1, Bastian Leibe1 and Tamon Sadasue2 1RWTH Aachen University, DE; 2RICOH Company LTD., JP Abstract Real-time identification of connected regions of pixels in large (e.g. FullHD) frames is a mandatory and expensive step in many computer vision applications that are becoming increasingly popular in embedded mobile devices such as smartphones, tablets and head mounted devices. Standard off-the-shelf embedded processors are not yet able to cope with the performance/flexibility trade-offs required by such applications. Therefore, in this work we present an Application Specific Instruction Set Processor (ASIP) tailored to concurrently execute thresholding, connected components labeling and basic feature extraction of image frames. The proposed architecture is capable to cope with frame complexities ranging from QCIF to FullHD frames with 1 to 4 bytes-per-pixel formats, while achieving an average frame rate of 30 frames-per-second (fps). Synthesis was performed for a standard 65nm CMOS library, obtaining an operating frequency of 350MHz and 2.1mm2 area. Moreover, evaluations were conducted both on typical and synthetic data sets, in order to thoroughly assess the achievable performance. Finally, an entire planar-marker based augmented reality application was developed and simulated for the ASIP. |
| 17:00 | 12.3.3 | IMAGE PROGRESSIVE ACQUISITION FOR HARDWARE SYSTEMS Speakers: Jianxiong Liu, Christos Bouganis and Peter Y.K. Cheung, Imperial College London, GB Abstract As the resolution of digital images increases, accessing raw image data from memory has become a major consideration during the design of image/video processing systems. This is due to the fact that the bandwidth requirement and energy consumption of such image accessing process has increased. Inspired by the successful application of progressive image sampling techniques in many image processing tasks, this work proposes to apply similar concept within hardware systems to efficiently trade image quality for reduced memory bandwidth requirement and lower energy consumption. Based on this idea, a hardware system is proposed that is placed between the memory subsystem and the processing core of the design. The proposed system alters the conventional memory access pattern to progressively and adaptively access pixels from a target memory external to the system. The sampled pixels are used to reconstruct an approximation to the ground truth, which is stored in an internal image buffer for further processing. The system is prototyped on FPGA and its performance evaluation shows that a saving of up to 85% of memory accessing time and 33%/45% of image acquisition time/energy is achieved on the benchmark image "lena" while maintaining a PSNR of about 30 dB. |
| 17:15 | 12.3.4 | HIGH-QUALITY REAL-TIME HARDWARE STEREO MATCHING BASED ON GUIDED IMAGE FILTERING Speakers: Christos Ttofis and Theocharis Theocharides, University of Cyprus, CY Abstract Stereo matching is a vital task in several emerging embedded vision applications requiring high-quality depth computation and real-time frame-rate. Although several stereo matching dedicated-hardware systems have been proposed in recent years, only few of them focus on balancing accuracy and speed. This paper proposes a hardware-based stereo matching architecture that aims to provide high accuracy and concurrently high performance in embedded vision applications. The proposed architecture integrates a compact and efficient design of the recently proposed guided image filter; an edge-preserving filter that reduces the hardware complexity of the implemented stereo algorithm, while at the same time maintains high-quality results. A prototype of the architecture has been implemented on a Kintex-7 FPGA board, achieving 60 fps for 720p resolution images. Moreover, the proposed design delivers leading accuracy when compared to state-of-the-art hardware implementations. |
| 17:30 | End of session | |