Date: Thursday 27 March 2014
Time: 11:00 - 12:30
Location / Room: Konferenz 3
Chair:
Frank Oppenheimer, OFFIS, DE
Co-Chair:
Todor Stefanov, Leiden University, NL
The first paper proposes a new static analysis approach based on segment graphs that identifies a tight set of potential access conflicts in segments that may-happen-in-parallel in system-level models. In the second paper, a technique for latency analysis for shared resource systems is introduced. The third paper proposes a method that improves the tradeoff between simulation speed and accuracy of performance models of architectures. Finally, the fourth paper deals with cross-correlating specification and RTL to discover versioning issues, poor documentation, and mismatches between specification and RTL.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 11:00 | 10.5.1 | (Best Paper Award Candidate) MAY-HAPPEN-IN-PARALLEL ANALYSIS BASED ON SEGMENT GRAPHS FOR SAFE ESL MODELS Speakers: Weiwei Chen1, Xu Han2 and Rainer Doemer3 1University of California, Irvine, US; 2Qualcomm Inc., US; 3EECS, UC Irvine, US Abstract A well-defined system-level model contains explicit parallelism and should be free from parallel access conflicts to shared variables. However, safe parallelism is difficult to achieve since risky shared variables are often hidden deep in the design and are not exposed through simulation. In this paper, we propose a new static analysis approach based on segment graphs that identifies a tight set of potential access conflicts in segments that may-happen-in-parallel (MHP). Our experimental results show that the analysis is complete, accurate and fast to reveal dangerous shared variables in several embedded application models. Compared to earlier work, our approach significantly reduces the number of false conflict reports and thus saves the designer time. |
| 11:30 | 10.5.2 | TIMING ANALYSIS OF FIRST-COME FIRST-SERVED SCHEDULED INTERVAL-TIMED DIRECTED ACYCLIC GRAPHS Speakers: Raymond Frijns1, Shreya Adyanthaya1, Sander Stuijk1, Jeroen Voeten1, Marc Geilen1, Ramon Schiffelers2 and Henk Corporaal1 1Eindhoven University of Technology, NL; 2ASML, NL Abstract Analyzing worst-case application timing for systems with shared resources is difficult, especially when non-monotonic arbitration policies like First-Come-First-Served (FCFS) scheduling are used in combination with varying task execution times. Analysis methods that conservatively analyze these systems are often based on state-space exploration, which is not scalable due to its inherent susceptibility to combinatorial explosion. We propose a scalable timing analysis method on periodically restarted Directed Acyclic Task Graphs, that can provide conservative bounds on task timing properties when shared resources with FCFS scheduling are used. By expressing task enabling and completion times in intervals, denoting best-case and worst-case timing properties, contention on the shared resources can be estimated using conservative approximations. With an industrial case study we show that our approach can easily analyze models with thousands of tasks in less than 10 seconds, and the worst-case bounds obtained show an average improvement of 46% compared to bounds obtained by static worst-case analysis. |
| 12:00 | 10.5.3 | A DYNAMIC COMPUTATION METHOD FOR FAST AND ACCURATE PERFORMANCE EVALUATION OF MULTI-CORE ARCHITECTURES Speakers: Sebastien Le Nours1, Adam Postula2 and Neil Bergmann2 1University of Nantes, FR; 2University of Queensland, AU Abstract Early estimation of performance has become necessary to facilitate design of complex multi-core architectures. Performance evaluation based on extensive simulations is time consuming and needs to be improved to allow exploration of different architectures in acceptable time. In this paper, we propose a method that improves the tradeoff between simulation speed and accuracy in performance models of architectures. This method computes during model execution some of the synchronization instants involved in architecture evolution. It allows grouping and abstracting architecture processes and this way significantly reduces the number of simulation events. Experiments show significant benefits from the computation method on the simulation time. Especially, a simulation speed-up by a factor of 4 is achieved in the considered case study, with no loss of accuracy about estimation of processing resource usage. The proposed method has potential to support automatic generation of efficient architecture models. |
| 12:15 | 10.5.4 | CROSS-CORRELATION OF SPECIFICATION AND RTL FOR SOFT IP ANALYSIS Speakers: Bhanu Singh1, Arunprasath Shankar1, Francis Wolff1, Christos Papachristou1, Daniel Weyer2 and Steve Clay2 1Case Western Reserve University, US; 2Rockwell Automation, US Abstract Semiconductor companies often use third-party IPs in order to improve their design productivity. In practice, there are risks involved in using a third-party IP as bugs may creep in due to versioning issues, poor documentation, and mismatches between specification and RTL. As a result of this, third-party IP specification and RTL must be carefully evaluated. Our methodology addresses this issue, which cross-correlates specification and RTL to discover these discrepancies. The key innovative ideas in our approach are to use prior and trusted experience about designs, which include their specs and RTL code. Also, we have captured this trusted experience into two knowledge bases (KB), Spec-KB and RTL-KB. Finally, knowledge base rules are used to cross-correlate the RTL blocks to the specs. We have tested our approach by analyzing several third-party IPs. We have defined metrics for specification coverage and RTL identification coverage to quantify our results. |
| 12:30 | End of session Lunch Break in Exhibition Area Sandwich lunch |