Date: Tuesday 19 March 2013
Time: 13:00 - 14:00
Location / Room: Auditorium Dauphine

Organiser:
Bernard Courtois, CMP, FR

Chair:
Enrico Macii, Politecnico di Torino, IT

The session presents the Ultra-Thin Body and Box (UTBB) Fully Depleted SOI (FDSOI) process and shows that it meets requirements for high-performance at low-power and high energy efficiency: the 28nm FDSOI, 14nm FDSOI, and 10nm FDSOI nodes, offer a practical and cost-effective roadmap to shrink features and enable a significant boost for "green" products. With unmatched access resistance and electrostatic characteristics, planar SOI is superior to other technologies based on bulk CMOS technology or FinFET architecture. Product silicon demonstrates outstanding performances for low-power applications in consumer electronics, including tablets and mobile phones. The session will address manufacturing capabilities, design infrastructure and future R&D roadmaps.

Time	Label	Presentation Title Authors
13:00	3.0.1	FDSOI: FROM SUCCESSFUL COLLABORATIVE R&D TO SUCCESSFUL SILICON RESULTS Author: Philippe Magarshack, STMicroelectronics, FR Abstract
13:20	3.0.2	DESIGN INFRASTRUCTURE TO SUPPORT ADVANCED FDSOI BELOW 20NM Author: Jean-Marc Talbot, Mentor Graphics R&D center in Grenoble, FR Abstract
13:40	3.0.3	ROADMAP TOWARDS 10NM FDSOI NODE Author: Laurent Malier, CEA-Leti, FR Abstract
14:00		End of session
16:00		Coffee Break in Exhibition Hall Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.