Agenda

Agenda

Further information is available at the workshop website.

Preliminary program

Agenda

Agenda

Agenda

Workshop Description

3D Integration is a promising technology for extending Moore's momentum in the next decennium, offering heterogeneous technology integration, higher transistor density, faster interconnects, and potentially lower cost and time-to-market. To produce 3D chips, new capabilities are needed: process technology, architectures, design methods and tools, and manufacturing test solutions. The goal of this Workshop is to bring together researchers, practitioners, and others interested in this exciting and rapidly evolving field, in order to update each other on the latest state-of-the-art, exchange ideas, and discuss future challenges.

The last four editions of this workshop took place in conjunction with DATE 2009 to DATE 2012.

• DATE 2009, Nice, France (https://www.date-conference.com/date09/conference/workshop-W5),
• DATE 2010, Dresden, Germany (https://www.date-conference.com/date10/conference/workshop-W5),
• DATE 2011, Grenoble, France (https://www.date-conference.com/date11/conference/workshop-W5).
• DATE 2012, Dresden, Germany (https://www.date-conference.com/date12/conference/session/W5).

The call for papers (CFP) for the upcoming workshop to be held in conjunction with DATE 2013 is available here.

Topic Areas

You are invited to participate and submit your contributions to the DATE 2013 Friday Workshop on 3D Integration. The areas of interest include (but are not limited to) the following topics:

• 3D technologies: chip-on-chip, micro-bumping, contactless, and through-silicon-vias interconnect
• TSV formation, perm./temp. wafer (de-)bonding
• 3D architectures and design space exploration
• 3D combinations of logic, memory, analog, RF
• Application, product, or test chip case studies
• 3D design methods and EDA tools
• Signal and power integrity, and ESD in 3D
• Thermo(-mechanical) analysis and -aware design
• Chip-package co-design for 3D
• Test, design-for-test, and debug techniques for 3D
• Wafer test access, KGD test, thin-wafer handling
• Economic benefit/cost trade-off studies
• Standardization initiatives

Submission Instructions

Submissions are invited in the form of (extended) abstracts not exceeding two pages. Submissions must be sent in as PDF file via the Welcome paper submission system: http://welcome.molesystems.com/DATE13-3D-WS/2013/. All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, and technical soundness. Selected submissions can be accepted for regular or poster presentation. At the workshop, an Electronic Workshop Digest will be made available to all workshop participants, which will include all material that authors are willing to provide: abstract, paper, slides, poster, etc.

The workshop program contains the following elements.

• One invited keynote address
• Two invited talk
• Two sessions with in total eight regular presentations
• Two poster sessions
• One panel session

Agenda

Agenda

Agenda

Agenda

Further information are available at the workshop website.

Organisers

Dr.-Ing. Diana Göhringer

Dr.-Ing. Göhringer works since 2001 in the domain of reconfigurable hardware. She graduated from the University of Karlsruhe in 2006 and finished her PhD at the Karlsruhe Institute of Technology (KIT) in 2011 with "summa cum laude". Since 2012, she leads the Young Investigator Group "CADEMA" at the KIT, where she focuses specifically on reconfigurable computing and multicore architectures. Dr. Göhringer is main- and coauthor of more than 40 highly relevant scientific papers in conferences, journals and book chapters.

Prof. Dr.-Ing. habil. Michael Hübner

Prof. Hübner is the Chair of Embedded Systems in Information Technology at the Ruhr-University of Bochum. He graduated at the University of Karlsruhe in 2003 and received his PhD in 2007 from the same University. He finished his habilitation in "reconfigurable computing systems" in 2011 at the Karlsruhe Institute of Technology (KIT). Prof. Hübner works since more than a decade in the domain of reconfigurable computing and is main- and coauthor of more than 130 scientific publications in highly relevant conference proceedings, journals and book chapters.

Description

Reconfigurable computing gained interest in the scientific and industrial community many years ago. It targeted the substitution of application specific integrated circuits (ASICs) by offering additional benefits, such as flexibility at design- and runtime. Since this time, various trends were followed and led to different generalizations and specializations e.g. through the offer of specific chips with more digital signal processing units or more logic cells or even embedded processors such as the Power PC 405 in Xilinx Virtex II Pro Field Programmable Gate Array (FPGA). In the meanwhile, other technologies such as Graphic Processing Units (GPUs) entered the marked and established themselves in the domain of high performance computing and nowadays also in embedded computing. However, the vendors of FPGAs continued improving the architectures, and the technology of their devices as well as the design tools and programming environments. Novel high performance architectures such as the Xilinx Zynq or Microsemi Smart Fusion, tailored for the embedded market, are some examples that the FPGA market is still growing. Virtual development platforms such as provided e.g. from Cadence enable an efficient design of complex systems without building a prototype in early stages of the development phase. Especially, this example shows how former hurdles will be bridged by introducing novel development tools for the chips which could be programmed in former times only by specialists. The introduction of novel technologies like MRAM, FRAM and also MEMRISTOR will further revolutionize the FPGA hardware and lead to a new era of reconfigurable computing.

This workshop will enable participants to take part in the most novel technology, architecture and design tools provided by the key players, but also from small and medium enterprises and researchers working at the cutting edge of technology. The unique constellation of the speakers which have sufficient time to talk about the novel chips will enable a deep insight into a promising reconfigurable computing future.

Confirmed speakers

• Dr. Ivo Bolsens, CTO Xilinx Inc., San Jose, US
• Steven Perry, Software Tools Architect, Altera, High Wycombe, UK
• Dr. Laurent Rougé, CEO and founder of Menta, Montpellier, FR
• Prof. Ahmed Jerraya, CEA Leti, Grenoble, FR
• Dr. Hichem Belhadj, VP Sales at Microsemi, US

Agenda

Agenda

Further infromation is availabel at the workshop website.

Preliminary Programme

Agenda

Agenda

Agenda

Poster session #1 and #2

On the computational role of astrocyte – neuron coupling in brain function
Liam McDaid and Jim Harkin (UniversityofUlster-UK)

Advances in Scalable Interconnect for Bio-Inspired Computational Platforms
Jim Harkin, Snaider Carrillo and Liam McDaid (University ofUlster -UK)

Experimental study of electrical Morris-Lecar neuron

Rachid Behdad¹, Stéphane Binczak¹, Vladimir I Nekorkin², Alexey S Dmitrichev² and Jean-Marie Bilbault¹ (¹Université de Bourgogne – FR, ²Institute of Applied Physics of RAS - RU)

Hardware architecture of Self-Organizing Maps
Laurent Rodriguez, Laurent Fiack and Benoît Miramond (ENSEA/ETIS - FR)

Validation of neural networks onto FPGA
Laurent Rodriguez¹, Laurent Fiack¹, Benoît Miramond¹ and Erik Hochapfel² (¹ENSEA/ETIS, ²Adacsys - FR)

A Neuromorphic VLSI Implementation of a Simplified Electrosensory System in a Weakly Electric Fish
Syed Ahmed Aamir, Jacob Engelmann, Leonel Gomez and Elisabetta Chicca (University ofBielefeld - DE)

Training Scheme Analysis for Memristor-Based Neuromorphic Design
Miao Hu¹, Hai Li¹, Qing Wu², Garrett S. Rose² and Yiran Chen¹ (¹University of Pittsburgh, ²Air Force Research Laboratory - US)

Bio-Inspired Artificial Olfactory System
Ping-Chen Huang and Jan Rabaey (UniversityofCaliforniaatBerkeley- US)

Event management for large scale event-driven digital hardware spiking neural networks
Louis-Charles Caron¹, Michiel D'Haene², Frédéric Mailhot³, Benjamin Schrauwen² and Jean Rouat³ (¹ENSTA ParisTech - FR, ²Universiteit Gent - BE, ³Université de Sherbrooke - CA)

Embedded Hardware Spiking Neural Network for UWB Bladder Volume Classification
Finn Krewer¹, Fearghal Morgan¹, Sandeep Pande¹, Martin O’halloran¹, Brian Mc Ginley¹, Seamus Cawley¹, Jim Harkin² and Liam Mc Daid² (¹National University of Ireland – IR, ²University of Ulster - UK)

Towards Formalization of Embedded Brain Reading
Elsa Andrea Kirchner and Rolf Drechsler (UniversityofBremen- DE)

Learning visual stimuli in neuromorphic VLSI
Federico Corradi¹, Massimiliano Giulioni², Vittorio Dante² and Paolo Del Giudice² (¹Institute of neuroinformatics - CH, ²Italian National Institute of Health - IT)

Design Exploration of EMBRACE Hardware Spiking Neural Network Architecture
Sandeep Pande and Fearghal Morgan (NationalUniversity ofIreland - IR)

A VLSI chip with spike-based synaptic plasticity for online learning in real-time
Fabio Stefanini¹, Mattia Rigotti², Stefano Fusi² and Giacomo Indiveri¹ (¹University of Zurich and ETHZ – CH, ²ColumbiaUniversity -US)

Brain Inspired Information Association on Hardware
Khadeer Ahmed, Wei Liu and Qinru Qiu (SyracuseUniversity- US)

Agenda

Agenda

Complementary Documentation

Will be provided before the event!