7.7 EMBEDDED TUTORIAL: From multi-core SoC to scale-out processors

Date: Wednesday 20 March 2013
Time: 14:30 - 16:00
Location / Room: Les Bans

Organiser:
Marcello Coppola, STMicroelectronics, FR

Chair:
Marcello Coppola, STMicroelectronics, FR

Co-Chair:
Luca Fanucci, University of Pisa, IT

Advanced computing is generally recognized as a way to accelerate progress in scientific research in the 21st Century. Heterogeneous multicore architecture has long been accepted within embedded computing the way to deliver improved performance and subsequent improved power efficiency. However to build a usable system within an affordable power budget both architectures and applications will need to change dramatically. These changes will impact all scales of computing from single MPSoC to racks to supercomputers. The entire computing industry faces the same power, memory, concurrency and programmability challenges. While Mobile, Consumer systems target the best tradeoff between area, performance and power, scale-out datacenters have additional challenges, notably performance per total cost of ownership (performance/TCO). Emerging applications (e.g., data serving and web search) that run in these datacenters operate on vast datasets that are not accommodated by on-die caches of existing server chips. Large caches reduce the die area available for cores and lower performance through long access latency when instructions are fetched. In tutorial, we will introduce the next generation multicore ARM based SoC to address the challenge of maintaining the homogeneity of the software architecture while extending to the benefits of heterogeneity. Then we will introduce the future evolutions of multi-core architectures in mobile and consumer SoCs, describing how gates will be used to meet the new application requirements. Finally, we introduce a methodology for designing scalable and efficient scale-out server processors that facilitates the design of optimal multi-core configurations, which divide the server processor's real estate into performance-optimal modules that couple many lean cores with a small last-level cache to maximize throughput per area given a power budget