Date: Tuesday 19 March 2013
Time: 17:00 - 18:30
Location / Room: Lesdigiueres (Exhibition Theatre)
Organiser:
Jürgen Haase, edacentrum, DE
Chair:
Jürgen Haase, edacentrum, DE
In this session industrial testimonials will offer engineers an insight into good working practices and state-of-the-art design methods of market leaders. This sessions features design centering of IO in 28nm FDSOI technology, SoC power integrity verification with focus on analogue/mixed signal macros, data management for future SoCs and evolutionary computation for validation, testing and design automation.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 17:00 | 4.8.1 | DESIGN CENTERING OF IO IN 28NM FDSOI TECHNOLOGY Author: Hubert Degoirat, STMicroelectronics, FR Abstract |
| 17:20 | 4.8.2 | USING APACHE REDHAWK FOR SOC POWER INTEGRITY VERIFICATION WITH FOCUS ON ANALOGUE/MIXED SIGNAL MACROS Author: Jack Kruppa, Infineon Technologies, DE Abstract |
| 17:40 | 4.8.3 | EVOLUTIONARY COMPUTATION FOR VALIDATION, TESTING AND DESIGN AUTOMATION Authors: Senad Durakovic and Aktan Burcin, Intel, US Abstract |
| 18:00 | 4.8.4 | DATA MANAGMENT IN FUTURE SOCS MADE EASY Author: Axel Jantsch, ELSIP, SE Abstract |
| 18:30 | End of session Evening Reception offered by the City of Grenoble in Several serving points inside the Exhibition Hall |