Topic: D7 Formal Methods and Verification

Formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem-proving, abstraction and refinement techniques, and real time verification); technologies supporting formal verification (including SMT, SAT, BDD, ATPG, and related work); semi-formal verification techniques; applications and case studies; formal verification of IPs, SoCs, cores and real-time/embedded systems; verification in practice, namely the integration of verification into the design flow.

Chair: Wolfgang Kunz, University of Kaiserslautern, DE, Contact

Co-Chair: Gianpiero Cabodi, Politecnico di Torino, IT, Contact

Members:

• bierejku [dot] at, Contact
• roderick [dot] bloemiaik [dot] tugraz [dot] at, Contact
• Alessandro Cimatti, FBK-irst (Fondazione Bruno Kessler - Center for Information technology), IT, Contact
• Joao Marques-Silva, University College Dublin, IE, Contact
• Fahim Rahim, Atrenta, FR, Contact